Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Meera Ravindranath, Subrata Banik, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#25).
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
soc/intel/alderlake: Revise PCIE port config
PCIE ClkSrcUsage and ClkSrcClkReq are always confusing in devicetree. Make it easier to just fill the number from schematics.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/romstage/fsp_params.c 4 files changed, 140 insertions(+), 77 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/25