Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39356 )
Change subject: mb/google/volteer: Enable Audio DSP UPD ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/39356/2/src/mainboard/google/voltee... File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/39356/2/src/mainboard/google/voltee... PS2, Line 121: # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T : register "PchHdaIDispLinkTmode" = "2" : # iDisp-Link Freq 4: 96MHz, 3: 48MHz. : register "PchHdaIDispLinkFrequency" = "4" : # Not disconnected/enumerable : register "PchHdaIDispCodecDisconnect" = "0"
Yes, as I remember this was the case on tglrvp. […]
We have never configured this before on previous platforms. I see that CML had the same UPDs but we never really touched those. So, I would like to understand if these are really required for volteer or if it is just the TGLRVP hardware configuration because of which you need it on tglrvp.
Can you check internally under what circumstances these UPDs need to be set? I couldn't find much documentation on this in EDS or FSP headers.