[coreboot-gerrit] Change in ...coreboot[master]: riscv: Use correct argument in a1 when invoking payload

[ron minnich (Code Review)]

ron minnich has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/31287 )

Change subject: riscv: Use correct argument in a1 when invoking payload
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riscv: Use correct argument in a1 when invoking payload

Fix a bug introduced by:
820dcfceb3901dbb00bb90c876e374126ca14e20
riscv: Simplify payload handling

Put fdt into a1 correctly.

Change-Id: I0dea7b88fde9d9a7365cb366917747d8110b9159
Signed-off-by: Philipp Hug 
Reviewed-on: https://review.coreboot.org/c/31287
Reviewed-by: ron minnich 
Tested-by: build bot (Jenkins) 
---
M src/arch/riscv/payload.c
1 file changed, 1 insertion(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  ron minnich: Looks good to me, approved

diff --git a/src/arch/riscv/payload.c b/src/arch/riscv/payload.c
index 8a07ff8..f3ed5a4 100644
--- a/src/arch/riscv/payload.c
+++ b/src/arch/riscv/payload.c
@@ -44,7 +44,7 @@
    write_csr(mepc, doit);
    asm volatile(
    	"mv a0, %0\n\t"
-		"mv a1, %0\n\t"
+		"mv a1, %1\n\t"
    	"mret" ::"r"(hart_id),
    	"r"(fdt)
    	: "a0", "a1");