[coreboot-gerrit] Change in coreboot[master]: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register

[Mario Scheithauer (Code Review)]

Mario Scheithauer has uploaded this change for review. ( https://review.coreboot.org/29530

Change subject: siemens/mc_apl3: Set Full Reset Bit into Reset Control Register
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siemens/mc_apl3: Set Full Reset Bit into Reset Control Register

This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 the PCH is driving SLP_S3
active (low).

Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer 
---
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/29530/1

diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
index f41fe73..13fa0f0 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
@@ -14,6 +14,7 @@
  */

#include <bootstate.h>
+#include <cf9_reset.h>
 #include <console/console.h>
 #include <device/pci_def.h>
 #include <device/pci_ids.h>
@@ -62,6 +63,11 @@
    	cmd |= PCI_COMMAND_MASTER;
    	pci_write_config16(dev, PCI_COMMAND, cmd);
    }
+
+	/* Set Full Reset Bit into Reset Control Register (I/O port CF9h).
+	 * When Bit 3 is set to 1 the PCH will driving SLP_S3 active (low).
+	 */
+	outb(FULL_RST, RST_CNT);
 }

static void wait_for_legacy_dev(void *unused)