[coreboot-gerrit] Change in coreboot[master]: tgl boards: Configure retimer Aux orientation

[Prashant Malani (Code Review)]

Prashant Malani has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39460 )

Change subject: tgl boards: Configure retimer Aux orientation
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Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/39460/4/src/mainboard/google/voltee... 
File src/mainboard/google/volteer/variants/baseboard/devicetree.cb:

https://review.coreboot.org/c/coreboot/+/39460/4/src/mainboard/google/voltee... 
PS4, Line 130: register "TcssAuxOri" = "0"
> I am not positive on the answer there let me find out but I assume it is controlled by FSP before wr […]

Great, thanks.
While you're at it, could you also check on how the register behavior is handled coming out of S3/S5? According to Aline this register gets reset when in S3/S5, so even if IOM_TYPEC_SW_CONFIG_3 is set for Port 0 to do SBU lane orientation in the SoC, that setting would get reset when we exit from S3/S5 (and the reset value looks to be to be 0, which means "retimer present". Is there a way to restore settings on reset?

If not, we may not be able to rely on this solution for SBU orientation configuration on the various ports in Volteer.