[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Set correct serirq mode

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/31536 )

Change subject: soc/intel/cannonlake: Set correct serirq mode
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soc/intel/cannonlake: Set correct serirq mode

Set FSP params PchSirqEnable/PchSirqMode based on board
setting of serirq_mode. Matches implementation on Skylake.

This is a no-change for existing boards since the default
remains SERIRQ_QUIET mode.

Tested on system76 galp3-c, out-of-tree WHL-U board

Change-Id: I9ad4f5a6c7391fc6e813ec1306c708f449a69f59
Signed-off-by: Jeremy Soller 
Signed-off-by: Matt DeVillier 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31536
Tested-by: build bot (Jenkins) 
Reviewed-by: Nico Huber 
Reviewed-by: Nathaniel L Desimone 
---
M src/soc/intel/cannonlake/chip.h
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/lpc.c
3 files changed, 10 insertions(+), 4 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, approved
  Nathaniel L Desimone: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h
index 330555c..b14c3c5 100644
--- a/src/soc/intel/cannonlake/chip.h
+++ b/src/soc/intel/cannonlake/chip.h
@@ -22,6 +22,7 @@
 #include <drivers/i2c/designware/dw_i2c.h>
 #include <intelblocks/gpio.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpc_lib.h>
 #include <smbios.h>
 #include <stdint.h>
 #include <soc/gpio.h>
@@ -360,6 +361,8 @@
     */
    uint8_t SerialIoDevMode[PchSerialIoIndexMAX];

+	enum serirq_mode serirq_mode;
+
    /* GPIO SD card detect pin */
    unsigned int sdcard_cd_gpio;

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 80918f1..9d6ed38 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -416,6 +416,10 @@
    /* Unlock all GPIO pads */
    tconfig->PchUnlockGpioPads = config->PchUnlockGpioPads;

+	/* Set correct Sirq mode based on config */
+	params->PchSirqEnable = config->serirq_mode != SERIRQ_OFF;
+	params->PchSirqMode = config->serirq_mode == SERIRQ_CONTINUOUS;
+
    /*
     * GSPI Chip Select parameters
     * The GSPI driver assumes that CS0 is the used chip-select line,
diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c
index c4eb884..8b98022 100644
--- a/src/soc/intel/cannonlake/lpc.c
+++ b/src/soc/intel/cannonlake/lpc.c
@@ -210,6 +210,8 @@

void lpc_soc_init(struct device *dev)
 {
+	const config_t *config = dev->chip_info;
+
    /* Legacy initialization */
    isa_dma_init();
    pch_misc_init();
@@ -218,10 +220,7 @@
    lpc_enable_pci_clk_cntl();

/* Set LPC Serial IRQ mode */
-	if (CONFIG(SERIRQ_CONTINUOUS_MODE))
-		lpc_set_serirq_mode(SERIRQ_CONTINUOUS);
-	else
-		lpc_set_serirq_mode(SERIRQ_QUIET);
+	lpc_set_serirq_mode(config->serirq_mode);

/* Interrupt configuration */
    pch_enable_ioapic(dev);