[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/common/lpc_lib: Add function to disable LPC Clock Run

[Nico Huber (Code Review)]

Nico Huber has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/29898

Change subject: soc/intel/common/lpc_lib: Add function to disable LPC Clock Run
......................................................................

soc/intel/common/lpc_lib: Add function to disable LPC Clock Run

Needed to fix up FSP-S bug on Apollo Lake.

Change-Id: If09fee07debb1f0de840b0c0bd7a65d338665f7c
Signed-off-by: Nico Huber 
---
M src/soc/intel/common/block/include/intelblocks/lpc_lib.h
M src/soc/intel/common/block/lpc/lpc_lib.c
2 files changed, 7 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/29898/1

diff --git a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
index e7b844f..a600f52 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpc_lib.h
@@ -97,6 +97,7 @@
 void lpc_set_serirq_mode(enum serirq_mode mode);
 /* Enable CLKRUN_EN for power gating LPC. */
 void lpc_enable_pci_clk_cntl(void);
+void lpc_disable_pci_clkrun(void);
 /*
 * Setup I/O Decode Range Register for LPC
 * ComA Range 3F8h-3FFh [2:0]
diff --git a/src/soc/intel/common/block/lpc/lpc_lib.c b/src/soc/intel/common/block/lpc/lpc_lib.c
index d27f877..0f26545 100644
--- a/src/soc/intel/common/block/lpc/lpc_lib.c
+++ b/src/soc/intel/common/block/lpc/lpc_lib.c
@@ -301,3 +301,9 @@
 {
    pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, LPC_PCCTL_CLKRUN_EN);
 }
+
+void lpc_disable_pci_clkrun(void)
+{
+	const u8 pcctl = pci_read_config8(PCH_DEV_LPC, LPC_PCCTL);
+	pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
+}