[coreboot-gerrit] Change in coreboot[master]: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init

[Elyes HAOUAS (Code Review)]

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/27558

Change subject: cpu/intel/model_f6x: Add model F6x for i945 parallel MP init
......................................................................

cpu/intel/model_f6x: Add model F6x for i945 parallel MP init

Change-Id: I62eedf2e6f1fd79fa3bf4e173e5317a7c775cdef
Signed-off-by: Elyes HAOUAS 
---
M src/cpu/intel/model_f6x/Makefile.inc
M src/cpu/intel/model_f6x/model_f6x_init.c
2 files changed, 4 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/27558/1

diff --git a/src/cpu/intel/model_f6x/Makefile.inc b/src/cpu/intel/model_f6x/Makefile.inc
index 855fc9e..8f4a282 100644
--- a/src/cpu/intel/model_f6x/Makefile.inc
+++ b/src/cpu/intel/model_f6x/Makefile.inc
@@ -1,4 +1,5 @@
 ramstage-y += model_f6x_init.c
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
+ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c

cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_f6x/microcode.bin
diff --git a/src/cpu/intel/model_f6x/model_f6x_init.c b/src/cpu/intel/model_f6x/model_f6x_init.c
index 496f563..194a528 100644
--- a/src/cpu/intel/model_f6x/model_f6x_init.c
+++ b/src/cpu/intel/model_f6x/model_f6x_init.c
@@ -27,7 +27,7 @@
    /* Turn on caching if we haven't already */
    x86_enable_cache();

-	if (!intel_ht_sibling()) {
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP) && !intel_ht_sibling()) {
    	/* MTRRs are shared between threads */
    	x86_setup_mtrrs();
    	x86_mtrr_check();
@@ -40,7 +40,8 @@
    setup_lapic();

/* Start up my CPU siblings */
-	intel_sibling_init(cpu);
+	if (!IS_ENABLED(CONFIG_PARALLEL_MP))
+		intel_sibling_init(cpu);
 };

static struct device_operations cpu_dev_ops = {