Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39795 )
Change subject: soc/intel/cnl: Fix `PcieClkSrcUsage` setting ......................................................................
Patch Set 1:
Patch Set 1:
Yeah, sorry, the commit message was stale. That's why the original, vanished? change was [WIP]. The actual problem with the for-loop is that it replaces Clock Source 0 with garbage, i.e. you can't configure 0 for any board because somebody took the weirdest shortcut, using the fact that unset devicetree options default to 0. But 0 is a valid value :-/
Yes, I noticed this some time back and found it really weird that value 0 cannot really be used. I have some thoughts on it. Let me see if I can write it down and propose some changes here.