[coreboot-gerrit] Change in coreboot[master]: soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/60732 )

Change subject: soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config
......................................................................

soc/intel/icl: Replace dt `HeciEnabled` by `CSE disable` config

Lists of changes:

1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables CSE based on the `HeciEnabled`
chip config with `DISABLE_CSE_AT_PRE_BOOT` config.

Mainboards that choose to make CSE enable during boot don't select
`cse disable` config.

Signed-off-by: Subrata Banik 
Change-Id: If4155e5c7eeb019f7dce59acd5b82720baddcb43
---
M src/soc/intel/icelake/chip.h
M src/soc/intel/icelake/smihandler.c
2 files changed, 1 insertion(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/60732/1

diff --git a/src/soc/intel/icelake/chip.h b/src/soc/intel/icelake/chip.h
index 9adc5b0..05ec99c 100644
--- a/src/soc/intel/icelake/chip.h
+++ b/src/soc/intel/icelake/chip.h
@@ -134,10 +134,6 @@

uint8_t Device4Enable;

-	/* HeciEnabled decides the state of Heci1 at end of boot
-	 * Setting to 0 (default) disables Heci1 and hides the device from OS */
-	uint8_t HeciEnabled;
-
    /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
    uint8_t eist_enable;

diff --git a/src/soc/intel/icelake/smihandler.c b/src/soc/intel/icelake/smihandler.c
index 2ca2816..a07aed7 100644
--- a/src/soc/intel/icelake/smihandler.c
+++ b/src/soc/intel/icelake/smihandler.c
@@ -16,11 +16,7 @@
  */
 void smihandler_soc_at_finalize(void)
 {
-	const struct soc_intel_icelake_config *config;
-
-	config = config_of_soc();
-
-	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
+	if (CONFIG(DISABLE_CSE_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
    	heci_disable();
 }