Patrick Georgi has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/30867 )
Change subject: mb/intel/glkrvp: Fix termination for dual voltage pins ......................................................................
mb/intel/glkrvp: Fix termination for dual voltage pins
These pins should not have pull downs configured in standby state as that can cause contention on the termination circuitry and lead to incorrect behavior as per Doc# 572688 Gemini Lake Processor GPIO Termination Configuration.
BUG=b:79982669 TEST=Checked that code compiles with changes.
Change-Id: I8156c67df152555ecf9e7be9e4851468538bcff1 Signed-off-by: Shamile Khan shamile.khan@intel.com Reviewed-on: https://review.coreboot.org/c/30867 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: John Zhao john.zhao@intel.corp-partner.google.com Reviewed-by: Furquan Shaikh furquan@google.com --- M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 1 file changed, 9 insertions(+), 9 deletions(-)
Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved John Zhao: Looks good to me, but someone else must approve
diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 94620432..03f2147 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -70,7 +70,7 @@ PAD_CFG_NF(GPIO_43, DN_20K, DEEP, NF1), /* GP_INTD_DSI_TE2 */ PAD_CFG_NF(GPIO_44, UP_20K, DEEP, NF1), /* USB_OC0_B */ PAD_CFG_NF(GPIO_45, UP_20K, DEEP, NF1), /* USB_OC1_B */ - PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, DN_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, UP_20K, DEEP, NF1, HIZCRx1, SAME), /* DSI_I2C_SDA */ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* DSI_I2C_SCL */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, UP_1K, DEEP, NF1), /* PMC_I2C_SDA */ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, UP_1K, DEEP, NF1), /* PMC_I2C_SCL */ @@ -136,7 +136,7 @@ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/*PMU_SLP_S4_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/*SUSPWRDNACK*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_104, UP_20K, DEEP, NF1),/*EMMC_DNX_PWR_EN_B*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, DN_20K, IGNORE, SAME),/*x4 Slot-2 Reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 0, DEEP, NONE, Tx0RxDCRx0, SAME),/*x4 Slot-2 Reset*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_106, UP_20K, DEEP, NF1),/*PMU_BATLOW_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_107, UP_20K, DEEP, NF1),/*PMU_RESETBUTTON_B*/ PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1),/*PMU_SUSCLK*/ @@ -159,33 +159,33 @@ PAD_CFG_NF_IOSSTATE(GPIO_125, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI0_DDC_SCL*/ PAD_CFG_NF_IOSSTATE(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SDA*/ PAD_CFG_NF_IOSSTATE(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0),/*HV_DDI1_DDC_SCL*/ - PAD_CFG_NF_IOSSTATE(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ - PAD_CFG_NF_IOSSTATE(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ + PAD_CFG_NF_IOSSTATE(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_VDDEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTEN*/ + PAD_CFG_NF_IOSSTATE(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0),/*PANEL0_BKLTCTL*/ PAD_CFG_NF_IOSSTATE(GPIO_131, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI0_HPD*/ PAD_CFG_NF_IOSSTATE(GPIO_132, UP_20K, DEEP, NF1, TxDRxE),/*HV_DDI1_HPD*/ PAD_CFG_NF_IOSSTATE(GPIO_133, UP_20K, DEEP, NF1, TxDRxE),/*HV_EDP_HPD*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-1 Power Enable*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, SAME),/*Slot-2 Power Enable*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, DN_20K, IGNORE, SAME),/*DGPU Power Select*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*DGPU Power Select*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, SAME),/*slot-1 Reset*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_138, UP_20K, DEEP, NF2, HIZCRx1, DISPUPD),/*SATA_GP0 (DC RTD3 need)*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_139, UP_20K, DEEP, NF2, TxLASTRxE, DISPUPD),/*SATA_GP1 (ZPODD_DEV_DET)*/ PAD_CFG_NF(GPIO_140, UP_20K, DEEP, NF5),/*SATA_DEVSLP0 (DC DEV SLP)*/ PAD_CFG_NF_IOSSTATE(GPIO_141, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_DEVSLP1 (ZPODD DEV ATN)*/ PAD_CFG_NF_IOSSTATE(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1),/*SATA_LED*/ - PAD_CFG_GPI_APIC_IOS(GPIO_143, DN_20K, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ + PAD_CFG_GPI_APIC_IOS(GPIO_143, NONE, DEEP, LEVEL, NONE, HIZCRx1, SAME),/*DGPU Power Ok*/ PAD_CFG_NF_IOSSTATE(GPIO_144, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_VDDEN*/ PAD_CFG_NF_IOSSTATE(GPIO_145, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTEN*/ PAD_CFG_NF_IOSSTATE(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1),/*PANEL1_BKLTCTL*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_157, 1, DEEP, UP_20K, IGNORE, SAME),/*WWAN_Reset/dGPS Reset*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, SAME),/*NFC_DFU*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, ENPD),/*NFC reset*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*NFC reset*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, UP_20K, IGNORE, SAME),/*SD_MODE for spk*/ PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, IGNORE, SAME),/*Touch panel reset*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_BCLK*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_WS_SYNC*/ - PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, UP_20K, TxDRxE, ENPD),/*Touch Panel Power Enable*/ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, NONE, Tx0RxDCRx0, SAME),/*Touch Panel Power Enable*/ PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, DN_20K, DEEP, NF1, HIZCRx1, SAME),/*AVS_I2S1_SDO*/
/* AUDIO COMMUNITY GPIOS*/