[coreboot-gerrit] Change in coreboot[master]: mb/intel/tglrvp: Enable SATA

[Wonkyu Kim (Code Review)]

Wonkyu Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38505 )

Change subject: mb/intel/tglrvp: Enable SATA
......................................................................

mb/intel/tglrvp: Enable SATA

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim 
Change-Id: I9f35682982a6c06522e58b0bbd7162ff02c37f32
---
M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
1 file changed, 5 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/38505/1

diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index fbd1c39..851b30e 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -45,6 +45,11 @@
    register "PcieClkSrcUsage[2]" = "0x3"
    register "PcieClkSrcUsage[3]" = "0x8"

+        register "SataEnable" = "1"
+        register "SataSalpSupport" = "1"
+        register "SataPortsEnable[0]" = "1"
+        register "SataPortsEnable[1]" = "1"
+
    register "SerialIoI2cMode" = "{
    	[PchSerialIoIndexI2C0]  = PchSerialIoPci,
    	[PchSerialIoIndexI2C1]  = PchSerialIoPci,