Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38514 )
Change subject: soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS ......................................................................
soc/intel/skylake: Update 64 bit SA DRAM bit fields as per SKL EDS
TEST=Build and boot EVE and Soraka to OS.
Change-Id: Ia32723444c044572fbcecce151d89e739e570b3b Signed-off-by: Subrata Banik subrata.banik@intel.com --- M src/soc/intel/skylake/acpi/systemagent.asl 1 file changed, 7 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/38514/1
diff --git a/src/soc/intel/skylake/acpi/systemagent.asl b/src/soc/intel/skylake/acpi/systemagent.asl index f826ba5..291c37b 100644 --- a/src/soc/intel/skylake/acpi/systemagent.asl +++ b/src/soc/intel/skylake/acpi/systemagent.asl @@ -32,26 +32,27 @@ Offset(0x40), /* EPBAR (0:0:0:40) */ EPEN, 1, /* Enable */ , 11, - EPBR, 20, /* EPBAR [31:12] */ + EPBR, 27, /* EPBAR [38:12] */
Offset(0x48), /* MCHBAR (0:0:0:48) */ MHEN, 1, /* Enable */ , 14, - MHBR, 17, /* MCHBAR [31:15] */ + MHBR, 24, /* MCHBAR [38:15] */
Offset(0x60), /* PCIEXBAR (0:0:0:60) */ PXEN, 1, /* Enable */ PXSZ, 2, /* PCI Express Size */ - , 23, - PXBR, 6, /* PCI Express BAR [31:26] */ + , 25, + PXBR, 11, /* PCI Express BAR [38:28] */
Offset(0x68), /* DMIBAR (0:0:0:68) */ DIEN, 1, /* Enable */ , 11, - DIBR, 20, /* DMIBAR [31:12] */ + DIBR, 27, /* DMIBAR [38:12] */
Offset (0x70), /* ME Base Address */ MEBA, 64, + Offset (0xa0), TOM, 64, /* Top of Used Memory */ TUUD, 64, /* Top of Upper Used Memory */ @@ -246,7 +247,7 @@ /* Get PCIe BAR */ Method (GPCB, 0, Serialized) { - ShiftLeft (_SB.PCI0.MCHC.PXBR, 26, Local0) + ShiftLeft (_SB.PCI0.MCHC.PXBR, 28, Local0) Return (Local0) }