Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48645 )
Change subject: soc/amd/cezanne: Add SMI support ......................................................................
Patch Set 7:
(4 comments)
https://review.coreboot.org/c/coreboot/+/48645/7/src/soc/amd/cezanne/include... File src/soc/amd/cezanne/include/soc/smi.h:
https://review.coreboot.org/c/coreboot/+/48645/7/src/soc/amd/cezanne/include... PS7, Line 9: 58 Isn't this 59?
https://review.coreboot.org/c/coreboot/+/48645/7/src/soc/amd/cezanne/include... PS7, Line 79: SMITYPE_PSP PPR says FakeSts0
https://review.coreboot.org/c/coreboot/+/48645/7/src/soc/amd/cezanne/include... PS7, Line 80: 34,35 FakeSts1,2.
https://review.coreboot.org/c/coreboot/+/48645/7/src/soc/amd/cezanne/include... PS7, Line 104: /* 59-63 Reserved */ : #define SMITYPE_KB_RESET 64 : #define SMITYPE_SLP_TYP 65 : #define SMITYPE_AL2H_ACPI 66 : /* 67-71 Reserved */ : #define SMITYPE_GBL_RLS 72 : #define SMITYPE_BIOS_RLS 73 : #define SMITYPE_PWRBUTTON_DOWN 74 : #define SMITYPE_SMI_CMD_PORT 75 : #define SMITYPE_USB_SMI 76 : #define SMITYPE_SERIRQ 77 : #define SMITYPE_SMBUS0_INTR 78 : /* 79-80 Reserved */ : #define SMITYPE_INTRUDER 81 : #define SMITYPE_VBAT_LOW 82 : #define SMITYPE_PROTHOT 83 : #define SMITYPE_PCI_SERR 84 : /* 85-89 Reserved */ : #define SMITYPE_EMUL60_64 90 : /* 91-132 Reserved */ : #define SMITYPE_FANIN0 133 : /* 134-140 Reserved */ : #define SMITYPE_CF9_WRITE 141 : #define SMITYPE_SHORT_TIMER 142 : #define SMITYPE_LONG_TIMER 143 : #define SMITYPE_AB_SMI 144 : /* 145 Reserved */ : #define SMITYPE_ESPI_SMI 146 : /* 147 Reserved */ : #define SMITYPE_IOTRAP0 148 : #define SMITYPE_IOTRAP1 149 : #define SMITYPE_IOTRAP2 150 : #define SMITYPE_IOTRAP3 151 : #define SMITYPE_MEMTRAP0 152 : /* 153-155 Reserved */ : #define SMITYPE_CFGTRAP0 156 : /* 157-159 Reserved */ Where are these defined in the PPR?