[coreboot-gerrit] Change in coreboot[master]: cpu/x86: Fix MSR_PLATFORM_INFO definition

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34090 )

Change subject: cpu/x86: Fix MSR_PLATFORM_INFO definition
......................................................................

cpu/x86: Fix MSR_PLATFORM_INFO definition

While common to many Intel CPUs, this is not an architectural
MSR that should be globally defined for all x86.

Change-Id: Ibeed022dc2ba2e90f71511f9bd2640a7cafa5292
Signed-off-by: Kyösti Mälkki 
---
M src/include/cpu/x86/tsc.h
M src/northbridge/intel/fsp_rangeley/udelay.c
2 files changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/34090/1

diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h
index 8dd9b75..dd333e8 100644
--- a/src/include/cpu/x86/tsc.h
+++ b/src/include/cpu/x86/tsc.h
@@ -11,8 +11,6 @@
 #define TSC_SYNC
 #endif

-#define MSR_PLATFORM_INFO 0xce
-
 struct tsc_struct {
    unsigned int lo;
    unsigned int hi;
diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c
index 01989ab..08301a3 100644
--- a/src/northbridge/intel/fsp_rangeley/udelay.c
+++ b/src/northbridge/intel/fsp_rangeley/udelay.c
@@ -18,6 +18,8 @@
 #include <cpu/x86/tsc.h>
 #include <cpu/x86/msr.h>

+#define MSR_PLATFORM_INFO 0xce
+
 /**
  * Intel Rangeley CPUs always run the TSC at BCLK = 100MHz
  */