[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Add method to modify GPIO community PM config

[Venkata Krishna Nimmagadda (Code Review)]

Venkata Krishna Nimmagadda has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40260 )

Change subject: soc/intel/tigerlake: Add method to modify GPIO community PM config
......................................................................

soc/intel/tigerlake: Add method to modify GPIO community PM config

This patch adds a two helper methods -

1. CGPM to configure GPIO power management bits that are part of
miscellaneous config. This is needed for configuraiton of these bits
based on s0ix entry and exit.

2. GPID to look up GPID community ID for an index. CGPM uses this ID
to configure the appropriate GPIO community

These methods are needed for implementing platform specific workarounds
to modify power management bits on s0ix entry and exit.

BUG=b:148892882
BRANCH=none
TEST="BUILD to check if it is successful"

Signed-off-by: Venkata Krishna Nimmagadda 
Change-Id: Iac3a269d3071eb5d4100d516249eeb5ce23c02fa
---
M src/soc/intel/tigerlake/acpi/gpio.asl
1 file changed, 49 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/40260/1

diff --git a/src/soc/intel/tigerlake/acpi/gpio.asl b/src/soc/intel/tigerlake/acpi/gpio.asl
index 2b4aff0..ed13468 100644
--- a/src/soc/intel/tigerlake/acpi/gpio.asl
+++ b/src/soc/intel/tigerlake/acpi/gpio.asl
@@ -142,3 +142,52 @@
    Local2 = PCRB(Local0) + PAD_CFG_BASE + (Local1 * 16)
    Return (Local2)
 }
+
+/*
+ * Return PCR Port ID of GPIO Communities
+ *
+ * Arg0: GPIO Community (0-5)
+ */
+Method (GPID, 1, Serialized)
+{
+	Switch (ToInteger (Arg0))
+	{
+		Case (0) {
+			Local0 = PID_GPIOCOM0
+		}
+		Case (1) {
+			Local0 = PID_GPIOCOM1
+		}
+		Case (2) {
+			Local0 = PID_GPIOCOM2
+		}
+		Case (4) {
+			Local0 = PID_GPIOCOM4
+		}
+		Case (5) {
+			Local0 = PID_GPIOCOM5
+		}
+		Default {
+			Return (0)
+		}
+	}
+
+	Return (Local0)
+}
+
+/*
+ * Configure GPIO Power Management bits
+ *
+ * Arg0: GPIO community (0-5)
+ * Arg1: PM bits in MISCCFG
+ */
+Method (CGPM, 2, Serialized)
+{
+	Local0 = GPID (Arg0)
+	If (Local0 != 0) {
+		/* Mask off current PM bits */
+		PCRA (Local0, GPIO_MISCCFG, ~(MISCCFG_ENABLE_GPIO_PM_CONFIG))
+		/* Mask in requested bits */
+		PCRO (Local0, GPIO_MISCCFG,  (Arg1 & MISCCFG_ENABLE_GPIO_PM_CONFIG))
+	}
+}