Attention is currently required from: Zheng Bao. Hello Zheng Bao,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/52756
to review the following change.
Change subject: amdfwtool: Allocate a little more space for each table ......................................................................
amdfwtool: Allocate a little more space for each table
The AMD tools need to replace or add FW(s) of an image. The total size of each table is specified in header and can not be changed, because the tools don't know what is outside the table. If the new table needs more space, the replacing can not be executed.
So we give some extra space for flexibility.
Change-Id: Id18db19c711b1ff7e694041408a5c4d30a9384ca Signed-off-by: Zheng Bao fishbaozi@gmail.com --- M util/amdfwtool/amdfwtool.c 1 file changed, 3 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/52756/1
diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 403785e..1435efe 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -71,6 +71,7 @@ #define BLOB_ALIGNMENT 0x100U #define TABLE_ERASE_ALIGNMENT _MAX(TABLE_ALIGNMENT, ERASE_ALIGNMENT) #define BLOB_ERASE_ALIGNMENT _MAX(BLOB_ALIGNMENT, ERASE_ALIGNMENT) +#define TABLE_REDUNDANCE (2 * TABLE_ALIGNMENT)
#define DEFAULT_SOFT_FUSE_CHAIN "0x1"
@@ -531,7 +532,7 @@ break; case PSP_COOKIE: case PSPL2_COOKIE: - table_size = ctx->current - dir->header.additional_info; + table_size = ctx->current - dir->header.additional_info + TABLE_REDUNDANCE; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The PSP table size should be 4K aligned\n"); exit(1); @@ -547,7 +548,7 @@ break; case BDT1_COOKIE: case BDT2_COOKIE: - table_size = ctx->current - bdir->header.additional_info; + table_size = ctx->current - bdir->header.additional_info + TABLE_REDUNDANCE; if ((table_size % TABLE_ALIGNMENT) != 0) { fprintf(stderr, "The BIOS table size should be 4K aligned\n"); exit(1);