[coreboot-gerrit] Change in ...coreboot[master]: coreboot: add post code for memory error from FSP

[Keith Short (Code Review)]

Keith Short has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/32773

Change subject: coreboot: add post code for memory error from FSP
......................................................................

coreboot: add post code for memory error from FSP

Add a new post code POST_RAM_FAILURE, used when the Intel FSP code fails
to initialize RAM.

BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms

Change-Id: Ibafefa0fc0b1c525f923929cc91731fbcc1e7533
Signed-off-by: Keith Short 
---
M src/drivers/intel/fsp1_1/raminit.c
M src/drivers/intel/fsp2_0/memory_init.c
M src/include/console/post_codes.h
3 files changed, 19 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/32773/1

diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c
index 726cc26..e91e49e 100644
--- a/src/drivers/intel/fsp1_1/raminit.c
+++ b/src/drivers/intel/fsp1_1/raminit.c
@@ -129,8 +129,10 @@
    timestamp_add_now(TS_FSP_MEMORY_INIT_END);

printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
-	if (status != EFI_SUCCESS)
+	if (status != EFI_SUCCESS) {
+		post_code(POST_RAM_FAILURE);
    	die("ERROR - FspMemoryInit failed to initialize memory!\n");
+	}

/* Locate the FSP reserved memory area */
    fsp_reserved_bytes = 0;
@@ -195,8 +197,10 @@
    }

#if CONFIG(DISPLAY_HOBS)
-	if (hob_list_ptr == NULL)
+	if (hob_list_ptr == NULL) {
+		post_code(POST_INVALID_FSP);
    	die("ERROR - HOB pointer is NULL!\n");
+	}

/*
     * Verify that FSP is generating the required HOBs:
@@ -274,14 +278,17 @@
    		printk(BIOS_DEBUG,
    			"0x%08x: Chipset reserved bytes reported by FSP\n",
    			(unsigned int)delta_bytes);
+			post_code(POST_INVALID_FSP);
    		die("Please verify the chipset reserved size\n");
    	}
 #endif
    }

/* Verify the FSP 1.1 HOB interface */
-	if (fsp_verification_failure)
+	if (fsp_verification_failure) {
+		post_code(POST_INVALID_FSP);
    	die("ERROR - coreboot's requirements not met by FSP binary!\n");
+	}

/* Display the memory configuration */
    report_memory_config();
diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c
index 879b477..bc0e538 100644
--- a/src/drivers/intel/fsp2_0/memory_init.c
+++ b/src/drivers/intel/fsp2_0/memory_init.c
@@ -317,6 +317,7 @@
    /* Handle any errors returned by FspMemoryInit */
    fsp_handle_reset(status);
    if (status != FSP_SUCCESS) {
+		post_code(POST_RAM_FAILURE);
    	printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status);
    	die("FspMemoryInit returned an error!\n");
    }
diff --git a/src/include/console/post_codes.h b/src/include/console/post_codes.h
index ce26aac..4b4226e 100644
--- a/src/include/console/post_codes.h
+++ b/src/include/console/post_codes.h
@@ -341,6 +341,14 @@
 #define POST_INVALID_FSP			0xE2

/**
+ * \brief RAM failure
+ *
+ * Set if RAM could not be initialized.  This includes RAM is missing,
+ * unsupported RAM configuration, or RAM failure.
+ */
+#define POST_RAM_FAILURE			0xE3
+
+/**
  * \brief TPM failure
  *
  * An error with the TPM, either unexepcted state or communications failure.