[coreboot-gerrit] Change in coreboot[master]: amd/pi/hudson: Convert 48Mhz en to read/write32

[John E. Kabat (Code Review)]

Hello Marshall Dawson,

I'd like you to do a code review. Please visit

https://review.coreboot.org/21033

to review the following change.

Change subject: amd/pi/hudson: Convert 48Mhz en to read/write32
......................................................................

amd/pi/hudson: Convert 48Mhz en to read/write32

Change-Id: I91e09757e5eea1eaf9b76921ad032ad2b79c14c5
Signed-off-by: Marshall Dawson 
---
M src/southbridge/amd/pi/hudson/early_setup.c
1 file changed, 4 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/21033/1

diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c
index b5e753d..ae8b406 100644
--- a/src/southbridge/amd/pi/hudson/early_setup.c
+++ b/src/southbridge/amd/pi/hudson/early_setup.c
@@ -260,18 +260,17 @@

void hudson_clk_output_48Mhz(void)
 {
-	u32 data, *memptr;
+	u32 ctrl;

/*
     * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so
     * 48Mhz will be on ball AP13 (FT3b package)
     */
-	memptr = (u32 *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40 );
-	data = *memptr;
+	ctrl = read32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40));

/* clear the OSCOUT1_ClkOutputEnb to enable the 48 Mhz clock */
-	data &= (u32)~(1<<2);
-	*memptr = data;
+	ctrl &= (u32)~(1<<2);
+	write32((void *)(ACPI_MMIO_BASE + MISC_BASE + FCH_MISC_REG40), ctrl);
 }

static uintptr_t hudson_spibase(void)