Attention is currently required from: Tim Wawrzynczak, Patrick Rudolph. build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/54334 )
Change subject: soc/intel/alderlake: Add configurable value for UsbTcPortEn ......................................................................
Patch Set 1:
(6 comments)
File src/soc/intel/alderlake/chip.h:
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/9cafc16f_4283d43a PS1, Line 44: * Specifies which Type-C Ports are enabled on the system code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/c3f1b92b_e976ba34 PS1, Line 45: * each bit represents a port starting at 0 code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/bb7d57d0_4ac4c002 PS1, Line 46: * Example: set value to 0x3 for ports 0 and 1 to be enabled code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/f2d66be8_84fc221d PS1, Line 47: */ code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/d216df58_1a597977 PS1, Line 48: uint8_t UsbTcPortEn; code indent should use tabs where possible
Robot Comment from checkpatch (run ID jenkins-coreboot-checkpatch-119381): https://review.coreboot.org/c/coreboot/+/54334/comment/d3f5a1f7_417864e3 PS1, Line 48: uint8_t UsbTcPortEn; please, no spaces at the start of a line