Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36915 )
Change subject: pcengines/apu2: Switch away from ROMCC_BOOTBLOCK ......................................................................
Patch Set 34:
(1 comment)
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... File src/mainboard/pcengines/apu2/romstage.c:
https://review.coreboot.org/c/coreboot/+/36915/30/src/mainboard/pcengines/ap... PS30, Line 66: pci_write_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE, data | 3);
We lost this in hudson/agesa|pi/early_setup. […]
Not exactly. LPC decode for SuperIO ports was never there actually. AGESA enables these decodes at some point, but for sure I couldn't configure UARTB on NCT5104d on apu2 before AmdInitReset, that is why decoding was being enabled here. To be safe with bootblock console init I have added this to southbridge bootblock init: https://review.coreboot.org/c/coreboot/+/37168/17/src/southbridge/amd/pi/hud...