[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs

[EricR Lai (Code Review)]

Attention is currently required from:  Felix Singer, Nico Huber, Furquan Shaikh, Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph.
EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49136 )

Change subject: soc/intel/alderlake: Refactor SoC code to maintain CPU and PCH PCIE RPs
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Patch Set 7:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/49136/comment/6a0c3a6e_09c39e88 
PS7, Line 12: 2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
> @Nico, this will deal in my patch :)

@Subrata, Furquan and I are working on it. So don't worry :p