[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp: Enable PMC support

[Marc Jones (Code Review)]

Marc Jones has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42289 )

Change subject: soc/intel/xeon_sp: Enable PMC support
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Patch Set 6:

(3 comments)

It looks like pmc.c has some ROMSTAGE ifdefs. I don't think that they are needed. I'm not sure why they are in the Skylake pmc.c, but they are not in the others socs. Maybe it was a SMI/powerbutton need for chromebook, but this patch doesn't seem to need it.

https://review.coreboot.org/c/coreboot/+/42289/6/src/soc/intel/xeon_sp/pmc.c 
File src/soc/intel/xeon_sp/pmc.c:

https://review.coreboot.org/c/coreboot/+/42289/6/src/soc/intel/xeon_sp/pmc.c... 
PS6, Line 11: console
move up to be in alphabetical order

https://review.coreboot.org/c/coreboot/+/42289/6/src/soc/intel/xeon_sp/pmc.c... 
PS6, Line 21: #if defined(__SIMPLE_DEVICE__)
Not needed if not built for ROMSTAGE

https://review.coreboot.org/c/coreboot/+/42289/6/src/soc/intel/xeon_sp/pmc.c... 
PS6, Line 35: ENV_RAMSTAGE
ROMSTAGE?