[coreboot-gerrit] Change in coreboot[master]: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU

[Johnny Lin (Code Review)]

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40523 )

Change subject: soc/xeon_sp: Read PPIN MSR and save to an array for each CPU
......................................................................

soc/xeon_sp: Read PPIN MSR and save to an array for each CPU

PPIN (Protected Processor Inventory Number) MSR is read and saved to an
array during xeon_sp_core_init() for each CPU for later use, such as
SMBIOS type 11 OEM string population.

Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin

Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47
---
M src/soc/intel/xeon_sp/skx/cpu.c
M src/soc/intel/xeon_sp/skx/include/soc/msr.h
2 files changed, 22 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/40523/1

diff --git a/src/soc/intel/xeon_sp/skx/cpu.c b/src/soc/intel/xeon_sp/skx/cpu.c
index fcee02f..7072285 100644
--- a/src/soc/intel/xeon_sp/skx/cpu.c
+++ b/src/soc/intel/xeon_sp/skx/cpu.c
@@ -25,8 +25,21 @@
 #include <assert.h>
 #include "chip.h"

+msr_t xeon_sp_ppin[MAX_SOCKET] = {0};
+static uint32_t core_bits, thread_bits;
+static uint32_t socket_index = (1 << MAX_SOCKET) - 1;
 static const config_t *chip_config = NULL;

+static void save_ppin(msr_t ppin, unsigned int apic_id)
+{
+	uint8_t package;
+
+	get_cpu_info_from_apicid(apic_id, core_bits, thread_bits, &package, NULL, NULL);
+	/* Save to the corresponding CPU PPIN. */
+	xeon_sp_ppin[package] = ppin;
+	socket_index &= ~(1UL << package);
+}
+
 static void xeon_configure_mca(void)
 {
    msr_t msr;
@@ -59,6 +72,10 @@
    	__func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id);
    assert(chip_config != NULL);

+	/* If socket_index is 0 then all PPIN have been saved. */
+	if (socket_index)
+		save_ppin(rdmsr(MSR_PPIN), cpu->path.apic.apic_id);
+
    /* set MSR_PKG_CST_CONFIG_CONTROL - scope per core*/
    msr.hi = 0;
    msr.lo = (PKG_CSTATE_NO_LIMIT | IO_MWAIT_REDIRECTION_ENABLE | CFG_LOCK_ENABLE);
@@ -246,7 +263,7 @@
    chip_config = dev->chip_info;

config_reset_cpl3_csrs();
-
+	get_core_thread_bits(&core_bits, &thread_bits);
    /* calls src/cpu/x86/mp_init.c */
    if (mp_init_with_smm(dev->link_list, &mp_ops) < 0)
    	printk(BIOS_ERR, "MP initialization failure.\n");
diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h
index 9505776..4f569e1 100644
--- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h
+++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h
@@ -17,6 +17,7 @@
 #define _SOC_MSR_H_

#include <intelblocks/msr.h>
+#include <cpu/x86/msr.h>

#define IA32_MCG_CAP                    0x179
 #define IA32_MCG_CAP_COUNT_MASK         0xff
@@ -109,4 +110,7 @@
 #define EPB_ENERGY_POLICY_SHIFT      3
 #define EPB_ENERGY_POLICY_MASK       (0xf << EPB_ENERGY_POLICY_SHIFT)

+/* MSR Protected Processor Inventory Number */
+#define MSR_PPIN		     0x04F
+extern msr_t xeon_sp_ppin[];
 #endif /* _SOC_MSR_H_ */