[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/geralt: Set up open-drain ChromeOS pins

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/73963 )

Change subject: mb/google/geralt: Set up open-drain ChromeOS pins
......................................................................

mb/google/geralt: Set up open-drain ChromeOS pins

Set open-drain GPIOs for ChromeOS as input and bias-disable mode.
After applying this patch, the voltage of these pins will become the
expected value 1.8V (previously 1.0V), preventing wrong judgement of
low/high.

Reference document:
MT8188G_GPIO_Formal_Application_Spec_V0.3

BUG=b:274058085
TEST=build pass

Change-Id: I057716df6c59efb84fc395109db022b82ce528c4
Signed-off-by: jason-ch chen 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73963
Reviewed-by: Yidi Lin 
Reviewed-by: Yu-Ping Wu 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/geralt/chromeos.c
M src/mainboard/google/geralt/gpio.h
2 files changed, 48 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Yu-Ping Wu: Looks good to me, approved
  Yidi Lin: Looks good to me, but someone else must approve

diff --git a/src/mainboard/google/geralt/chromeos.c b/src/mainboard/google/geralt/chromeos.c
index ab9f1d6..a6e8917 100644
--- a/src/mainboard/google/geralt/chromeos.c
+++ b/src/mainboard/google/geralt/chromeos.c
@@ -12,8 +12,19 @@
 {
    /* Set up open-drain pins */
    gpio_input(GPIO_EC_AP_INT_ODL);
+	gpio_input(GPIO_EC_AP_HID_INT_ODL);
+	gpio_input(GPIO_EC_AP_RSVD0_ODL);
    gpio_input(GPIO_GSC_AP_INT_ODL);
    gpio_input(GPIO_AP_WP_ODL);
+	gpio_input(GPIO_EDP_HPD_1V8);
+	gpio_input(GPIO_EC_AP_HPD_OD);
+	gpio_input(GPIO_PCIE_WAKE_1V8_ODL);
+	gpio_input(GPIO_PCIE_CLKREQ_1V8_ODL);
+	gpio_input(GPIO_SAR_INT_ODL);
+	gpio_input(GPIO_SD_CD_ODL);
+	gpio_input(GPIO_HP_INT_ODL);
+	gpio_input(GPIO_SPKR_INT_ODL);
+	gpio_input(GPIO_TCHSCR_INT_1V8_L);

/* Set up GPOs */
    gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0);
@@ -21,6 +32,7 @@
    gpio_output(GPIO_RST_SPKR_L, 0);
    gpio_output(GPIO_XHCI_INIT_DONE, 0);
    gpio_output(GPIO_BEEP_ON_OD, 0);
+	gpio_output(GPIO_MT7921_PMU_EN_1V8, 0);
 }

void fill_lb_gpios(struct lb_gpios *gpios)
diff --git a/src/mainboard/google/geralt/gpio.h b/src/mainboard/google/geralt/gpio.h
index c05b804..ea8ec53 100644
--- a/src/mainboard/google/geralt/gpio.h
+++ b/src/mainboard/google/geralt/gpio.h
@@ -10,15 +10,26 @@
 #define GPIO_AP_WP_ODL		GPIO(GPIO15)
 #define GPIO_BEEP_ON_OD		GPIO(KPROW0)
 #define GPIO_EC_AP_INT_ODL	GPIO(DPI_DE)
+#define GPIO_EC_AP_HPD_OD	GPIO(DPTX_HPD)
+#define GPIO_EC_AP_HID_INT_ODL	GPIO(DPI_VSYNC)
+#define GPIO_EC_AP_RSVD0_ODL	GPIO(MSDC2_DAT1)
 #define GPIO_EN_SPKR		GPIO(I2SIN_D1)
 #define GPIO_GSC_AP_INT_ODL	GPIO(GPIO00)
 #define GPIO_RST_SPKR_L		GPIO(I2SO2_D1)
 #define GPIO_XHCI_INIT_DONE	GPIO(DPI_CK)
+#define GPIO_SAR_INT_ODL	GPIO(USB1_VBUS_VALID)
+#define GPIO_HP_INT_ODL		GPIO(I2SIN_BCK)
+#define GPIO_SPKR_INT_ODL	GPIO(I2SIN_WS)

#define GPIO_I2SI1_LRCK		GPIO(I2SO2_D2)
 #define GPIO_I2SI1_BCK		GPIO(I2SIN_D3)
 #define GPIO_I2SO1_D0		GPIO(GPIO11)

+#define GPIO_PCIE_WAKE_1V8_ODL		GPIO(PCIE_WAKE_N)
+#define GPIO_PCIE_CLKREQ_1V8_ODL	GPIO(PCIE_CLKREQ_N)
+#define GPIO_TCHSCR_INT_1V8_L		GPIO(DPI_D12)
+#define GPIO_MT7921_PMU_EN_1V8		GPIO(DPI_D14)
+
 #define GPIO_EDP_BL_PWM_1V8		GPIO(DISP_PWM1)
 #define GPIO_EDP_HPD_1V8		GPIO(GPIO17)
 #define GPIO_EN_PP3300_EDP_DISP_X	GPIO(DSI1_LCM_RST)