Attention is currently required from: Tarun Tuli, Paul Menzel, Ivy Jian, Maximilian Brune, Angel Pons, Ronak Kanabar.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74158 )
Change subject: soc/intel/cmn/cpu: Add function to disable 3-strike CATERR ......................................................................
Patch Set 4:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74158/comment/40e1f163_aed1b321 PS3, Line 8:
I would directly write the whole thing (makes it easier to understand for me personally): "Detectable but Uncorrected Errors (DUE) can manifest themselves via blue screens or other system hangs/crashes. In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a three-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. Identifying the root cause of such events is notoriously difficult, as the system is effectively wedged and cannot be put into probe mode by JTAG-assisted hardware debuggers. In such extreme cases the machine check error handler at vector 0x18h does not execute correctly and no register information is captured." source: https://www.asset-intertech.com/resources/blog/2015/12/catastrophic-errors-i...
Sorry! I don't understand what is the point of adding those details? I'm not here to explain what 3-stick error mean/does. One can refer to the appropriate document for that.
I'm intended to enable a bit which is described in the EDS. I don't think for enabling the bit related to 3-strike, I need to write whole paragraph about what is 3-strike error.
I have wrote the commit msg to explain what this patch does
``` This patch prevents the Three Strike Counter from incrementing, which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. ```
If I have to do a PCI BAR programming does that mean, I have to explain what is PCI and it's internal details ?