[coreboot-gerrit] Change in coreboot[master]: soc/intel/apollolake: Provide the option to enable DDR 2x refresh rate

[Gaggery Tsai (Code Review)]

Attention is currently required from: Marx Wang.
Gaggery Tsai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48510 )

Change subject: soc/intel/apollolake: Provide the option to enable DDR 2x refresh rate
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Patch Set 13: Code-Review-1

(1 comment)

Patchset:

PS13: 
Should we wait a little bit? It looks to me the CONFIG would impact all DRAMs. Since the mitigation is for DRAM, does it make sense to add an attribute in lpddr4_sku like "bool row_hammer_mitigation"?

So in mainboard, just an example, we could initialize the variable if this DRAM is impacted like
        [0] = {
                .speed = LP4_SPEED_2400,
                .ch0_rank_density = LP4_8Gb_DENSITY,
                .ch1_rank_density = LP4_8Gb_DENSITY,
                .ch0_dual_rank = 1,
                .ch1_dual_rank = 1,
                .part_num = "K4F6E304HB-MGCJ",
                .row_hammer_mitigation = CONFIG(ENABLE_2X_MITIGATION)
        },
        /* K4F8E304HB-MGCJ - both logical channels  */
        .....

This setting will be passed to set_lpddr4_defaults with the slightly change to the meminit_lpddr4 with sku->row_hammer_mitigation.