[coreboot-gerrit] Change in coreboot[master]: [WIP] tigerlake: add TCC activation functionality

[Sumeet R Pawnikar (Code Review)]

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41855 )

Change subject: [WIP] tigerlake: add TCC activation functionality
......................................................................

[WIP] tigerlake: add TCC activation functionality

This enables to configure the Thermal Control Circuit (TCC) activation
value to new value as tcc_offset in degree Celcius. It prevents any
abrupt thermal shutdown while running heavy workload. This helps to
take early thermal throttling action before CPU temperature reaches
maximum operating temperature TjMax value.

BUG=None
BRANCH=None
TEST=Built for volteer platform and verified the MSR value.

Change-Id: I37dd878902b080602d70c5c3c906820613ea14a5
Signed-off-by: Sumeet R Pawnikar 
---
M src/soc/intel/tigerlake/cpu.c
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 26 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/41855/1

diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c
index f5870ec..a61e431 100644
--- a/src/soc/intel/tigerlake/cpu.c
+++ b/src/soc/intel/tigerlake/cpu.c
@@ -30,6 +30,26 @@
    fsps_load(romstage_handoff_is_resume());
 }

+static void configure_thermal_target(void)
+{
+	config_t *conf = config_of_soc();
+	msr_t msr;
+
+	/* Set TCC activation offset */
+	msr = rdmsr(MSR_PLATFORM_INFO);
+	if ((msr.lo & (1 << 30)) && conf->tcc_offset) {
+		msr = rdmsr(MSR_TEMPERATURE_TARGET);
+		msr.lo &= ~(0xf << 24);
+		msr.lo |= (conf->tcc_offset & 0xf) << 24;
+		wrmsr(MSR_TEMPERATURE_TARGET, msr);
+	}
+	msr = rdmsr(MSR_TEMPERATURE_TARGET);
+	/* Time Window Tau Bits [6:0] */
+	msr.lo &= ~0x7f;
+	msr.lo |= 0xe6; /* setting 100ms thermal time window */
+	wrmsr(MSR_TEMPERATURE_TARGET, msr);
+}
+
 static void configure_isst(void)
 {
    config_t *conf = config_of_soc();
@@ -216,4 +236,7 @@
 {
    if (mp_init_with_smm(cpu_bus, &mp_ops))
    	printk(BIOS_ERR, "MP initialization failure.\n");
+
+	/* Thermal throttle activation offset */
+	configure_thermal_target();
 }
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index bdcd357..1aeddd6 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -205,6 +205,9 @@
    /* Enable TCPU for processor thermal control */
    params->Device4Enable = config->Device4Enable;

+	/* Set TccActivationOffset */
+	params->TccActivationOffset = config->tcc_offset;
+
    /* LAN */
    dev = pcidev_path_on_root(PCH_DEVFN_GBE);
    if (!dev)