[coreboot-gerrit] Change in coreboot[master]: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/48270 )

Change subject: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller
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soc/amd/picassso/acpi: increase MMIO region size of GPIO controller

The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.

Also replace the base GPIO address with the corresponding define.

Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) 
Reviewed-by: Marshall Dawson 
---
M src/soc/amd/picasso/acpi/sb_fch.asl
1 file changed, 2 insertions(+), 2 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Marshall Dawson: Looks good to me, approved

diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl
index 6cbfc5f..c4dffed 100644
--- a/src/soc/amd/picasso/acpi/sb_fch.asl
+++ b/src/soc/amd/picasso/acpi/sb_fch.asl
@@ -34,7 +34,7 @@
    			ActiveLow,
    			Exclusive, , , IRQR)
    		{ 0 }
-			Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+			Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
    	}
    	CreateDWordField (Local0, IRQR._INT, IRQN)
    	If (PMOD) {
@@ -44,7 +44,7 @@
    	}
    	If (IRQN == 0x1f) {
    		Return (ResourceTemplate() {
-				Memory32Fixed (ReadWrite, 0xFED81500, 0x300)
+				Memory32Fixed (ReadWrite, ACPIMMIO_GPIO0_BASE, 0x400)
    		})
    	} Else {
    		Return (Local0)