Michał Żygowski has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36914 )
Change subject: binaryPI: implement C bootblock ......................................................................
Patch Set 8:
(1 comment)
Patch Set 8:
(1 comment)
Patch Set 8:
This patchset works with apu2 C bootblock change. However still can not move to SOC_AMD_COMMON_BLOCK_CAR, thus added implementation to drivers/amd/agesa/cahce_as_ram.S .
Problems with SOC_AMD_COMMON_BLOCK_CAR:
- either frozen at postcode A2
- or reset loop in AmdInitReset
Possible reasons:
- FPU and SSE initialization missing in SOC_AMD_COMMON_BLOCK_CAR path
- BSP stack setup to _ecar_stack missing in SOC_AMD_COMMON_BLOCK_CAR
you probably want to set %esp to _ecar_stack on SOC_AMD_COMMON_BLOCK_CAR too.
I thought about it. I will send a patch outside the relation chain and ask for testing (I do not have stoneyridge TBH).
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... File src/drivers/amd/agesa/cache_as_ram.S:
https://review.coreboot.org/c/coreboot/+/36914/8/src/drivers/amd/agesa/cache... PS8, Line 142: OSFXSR [
Is done in arch/x86/bootblock_crt0.S if CONFIG_SSE is set. […]
Right. Would it be feasible to add it to bootblock_crt0.S? And most important, why bootblock_crt0 doesn't clear the FPU emulation bit? In fact I have copied this comment from cpu/x86/fpu_enable.inc and I wonder how true this statement is with #UD