[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Intel Xeon Scalable Processor support

[Anjaneya "Reddy" Chagam (Code Review)]

Anjaneya "Reddy" Chagam has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )

Change subject: soc/intel: Add Intel Xeon Scalable Processor support
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Patch Set 42:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
PS41, Line 33: 		.CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
             : 		.CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
> lets not use this. […]

No it doesn't make sense to set them to zero. Let FSP TempRamInit do its job of setting MTTR. It does hang w/ both SKX FSP and CPX FSP. This is really not desirable to change.