[coreboot-gerrit] [S] Change in coreboot[master]: soc/intel/cmn/cse: Handle unnecessary End-Of-Post

[Jérémy Compostella (Code Review)]

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74205 )

Change subject: soc/intel/cmn/cse: Handle unnecessary End-Of-Post
......................................................................

soc/intel/cmn/cse: Handle unnecessary End-Of-Post

BUG:b/276927816
BRANCH=firmware-brya-14505.B
TEST=local tests - TBD

Change-Id: Id2d23df668ab698213e8b1af652ef9b90ccad046
Signed-off-by: Jeremy Compostella 
---
M src/soc/intel/common/block/cse/cse_eop.c
1 file changed, 21 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74205/1

diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c
index 16cf523..1317a72 100644
--- a/src/soc/intel/common/block/cse/cse_eop.c
+++ b/src/soc/intel/common/block/cse/cse_eop.c
@@ -19,6 +19,7 @@
    CSE_CMD_RESULT_ERROR,
    CSE_CMD_RESULT_DISABLED,
    CSE_CMD_RESULT_RETRY,
+	CSE_CMD_RESULT_SKIP,
 };

static enum cse_cmd_result decode_heci_send_receive_error(enum cse_tx_rx_status ret)
@@ -131,7 +132,7 @@
        cse_is_hfs1_com_soft_temp_disable()) {
    	printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT "
    	       "TEMP DISABLE state, skipping EOP\n");
-		return CSE_CMD_RESULT_SUCCESS;
+		return CSE_CMD_RESULT_SKIP;
    }

/*
@@ -259,6 +260,9 @@
    	ret = cse_send_cmd_retries(cse_send_eop);
    	if (ret == CSE_CMD_RESULT_SUCCESS)
    		eop_sent = true;
+		/* End-Of-Post is not needed. */
+		if (ret == CSE_CMD_RESULT_SKIP)
+			goto done;
    }

if (!wait_for_completion)
@@ -270,8 +274,9 @@
    	ret = cse_send_cmd_retries(cse_send_and_receive_eop);
    	handle_cse_eop_result(ret);
    }
-	timestamp_add_now(TS_ME_END_OF_POST_END);

+done:
+	timestamp_add_now(TS_ME_END_OF_POST_END);
    set_cse_device_state(PCH_DEVFN_CSE, DEV_IDLE);

eop_complete = true;