[coreboot-gerrit] [S] Change in coreboot[main]: util/cbfstool: Place XIP components and FIT at high flash addresses

[Shuo Liu (Code Review)]

Attention is currently required from: Andrey Petrov, Angel Pons, Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Intel coreboot Reviewers, Johnny Lin, Jonathan Zhang, Julius Werner, Patrick Rudolph, Ronak Kanabar, Tim Chu, Yu-Ping Wu.

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/86570?usp=email )

Change subject: util/cbfstool: Place XIP components and FIT at high flash addresses
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Patch Set 9:

(2 comments)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86570/comment/b88cd1d3_7309c6f4?usp... :
PS8, Line 9: CACHE_ROM_SIZE
> Does GNR not support caching more than 16 MiB of flash?

Cache as ram working on non-evict mode, or in-another word, if contents are evicted, due to backend memory is not ready, the content will be lost, thus cause program break if referenced later. GNR is not allowed to use more than 16MiB (UEFI actually only use 5MiB).

https://review.coreboot.org/c/coreboot/+/86570/comment/fef7d6b6_9c351126?usp... :
PS8, Line 17: Select XIP_AT_HIGH_ADDR for intel Granite Rapids SoC.
> What is the impact of this change? Faster boot times?

Right. Otherwise the boot time will be unaccepted slow.