[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Correct TCSS XHCI Port status offset

[Subrata Banik (Code Review)]

Attention is currently required from: Maulik V Vaghela, Tim Wawrzynczak, Sridhar Siricilla, Balaji Manigandan, Deepti Deshatty, Patrick Rudolph.
Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55230 )

Change subject: soc/intel/alderlake: Correct TCSS XHCI Port status offset
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Patch Set 3:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/55230/comment/db11ae8f_a03b61d9 
PS3, Line 10: captured from the ADL-P Processor EDS Volume 2b of 2(DOC ID:619503).
can u also capture that you have modified TCSS_XHCI_USB2_PORT_NUM as well in the same CL?