Sumeet R Pawnikar (sumeet.r.pawnikar@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17730
-gerrit
commit ff9f2190ccfc9b264f71ffa276238e8c3afaec8b Author: Sumeet Pawnikar sumeet.r.pawnikar@intel.com Date: Mon Dec 5 16:56:15 2016 +0530
mainboard/google/reef: Set PL2 override to 15000mW
This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:60535 TEST=Built, booted on reef and verified PL2 value.
Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index fa097fd..49c1ba6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -53,6 +53,8 @@ chip soc/intel/apollolake # current VR solution. Experiments show that SoC TDP max (6W) can # be reached when RAPL PL1 is set to 12W. register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000"
# Enable Audio Clock and Power gating register "hdaudio_clk_gate_enable" = "1"