Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/47182 )
Change subject: soc/intel/tigerlake: Add PCH PCIe RPs wake up events to event log ......................................................................
Patch Set 2:
(1 comment)
here's a weird error: ``` vboot SHA256 built with tight loops (slower, smaller code size) CREATE GBB (without BMPFV) make[1]: /cb-build/coreboot-gerrit.0/default/sharedutils/futility/futility: Permission denied make[1]: *** [src/security/vboot/Makefile.inc:242: /cb-build/coreboot-gerrit.0/default/GOOGLE_DEDEDE/gbb.stub] Error 127 make[1]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit'
```
https://review.coreboot.org/c/coreboot/+/47182/1/src/soc/intel/tigerlake/elo... File src/soc/intel/tigerlake/elog.c:
https://review.coreboot.org/c/coreboot/+/47182/1/src/soc/intel/tigerlake/elo... PS1, Line 53: PCIE_ROOT_PORT_STATUS
Should we be using pci_dev_is_wake_source() instead of checking PCIE_ROOT_PORT_STATUS?
Ah yes, that simplifies this; I had forgotten that there was a capability reg for PM.