[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Provide interface to update TCC offset

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30803 )

Change subject: soc/intel/cannonlake: Provide interface to update TCC offset
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Patch Set 1:

(1 comment)

https://review.coreboot.org/#/c/30803/1/src/soc/intel/cannonlake/cpu.c 
File src/soc/intel/cannonlake/cpu.c:

https://review.coreboot.org/#/c/30803/1/src/soc/intel/cannonlake/cpu.c@186 
PS1, Line 186: 	msr.lo |= 0xe6; /* setting 100ms thermal time window */
Is there public docs for this MSR? I find it odd the mask is 6:0 but you set also bit 7 here. Maybe its fine.