Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36221 )
Change subject: WIP: Add configurable ramstage support for minimal PCI scanning ......................................................................
Patch Set 14:
So have we gone from wanting to not assign resources for certain devices to not assigning resources for almost all devices unless someone explicitly changes the code?
1. I don't think that was our original problem. At least for USB4/thunderbolt there's a finite set of viddids we can purposefully not allocate resources for.
2. Then that leaves people plugging in GPU(s) with large amount of resources. That's a different problem, and I assume we can solve that by pushing those into 64-bit address space. I'm hand waving some details that we may need to add, but I think that solves that problem.
I think I can envision a path for 1 and 2 and seems fairly straight forward. But if one wants coreboot *not* to assign any resources I think that just complicates matters w.r.t. __pci_drivers and other implicit expectations. Is one just going to knock down all the pci command registers for every visible pci device prior to jumping to payload? That seems cleaner from an implementation perspective, but I think that's going to lead to unintended issues. Should we tweak such a notion and do it only for devces (and their parent) on secondary buses?