Lijian Zhao (lijian.zhao@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14288
-gerrit
commit e9d5cae3670700134d7ebd271f11371c9a83f342 Author: Zhao, Lijian lijian.zhao@intel.com Date: Thu Apr 7 15:50:03 2016 -0700
[Fixup]soc/intel/apollolake: Fix northbridge _CRS
Fix build break on current _CRS method with correct scope.
Change-Id: I75ba8abc547ec69be0a0950e23a7c31b447af31e Signed-off-by: Zhao, Lijian lijian.zhao@intel.com --- src/soc/intel/apollolake/acpi/northbridge.asl | 96 +++++++++++++-------------- 1 file changed, 48 insertions(+), 48 deletions(-)
diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 1349c6a..6ad96ec 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -19,18 +19,18 @@ Device (MCHC) { Name (_ADR, 0x00000000) /*Dev0 Func0 */
- OperationRegion (MCHP, PCI_Config, 0x00, 0x100) - Field (MCHP, DWordAcc, NoLock, Preserve) - { - Offset(0x60), - MCNF, 32, /* PCI MMCONF base */ - Offset (0xA8), - TUUD, 64, /* Top of Upper Used Memory */ - Offset(0xB4), - BGSM, 32, /* Base of Graphics Stolen Memory */ - Offset(0xBC), - TLUD, 32, /* Top of Low Useable DRAM */ - } + OperationRegion (MCHP, PCI_Config, 0x00, 0x100) + Field (MCHP, DWordAcc, NoLock, Preserve) + { + Offset(0x60), + MCNF, 32, /* PCI MMCONF base */ + Offset (0xA8), + TUUD, 64, /* Top of Upper Used Memory */ + Offset(0xB4), + BGSM, 32, /* Base of Graphics Stolen Memory */ + Offset(0xBC), + TLUD, 32, /* Top of Low Useable DRAM */ + } Name (MCRS, ResourceTemplate() { /* Bus Numbers */ @@ -76,51 +76,51 @@ Device (MCHC) NonCacheable, ReadWrite, 0x00000000, 0x10000, 0x1ffff, 0x00000000, 0x10000,,, PM02) -}) + })
-/* Current Resource Settings */ -Method (_CRS, 0, Serialized) -{ + /* Current Resource Settings */ + Method (_CRS, 0, Serialized) + {
- /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN)
- /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^MCHC.TLUD, 0xFFF00000, PMIN) - /* Read MMCONF base */ - And(^MCHC.MCNF, 0xF0000000, PMAX) + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCNF, 0xF0000000, PMAX)
- /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN)
- /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN)
- /* Read BGSM */ - And(^MCHC.BGSM, 0xFFF00000, GMIN) + /* Read BGSM */ + And(^BGSM, 0xFFF00000, GMIN)
- /* Read TOLUD */ - And(^MCHC.TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + /* Read TOLUD */ + And(^TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN)
- /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN)
- Store (^MCHC.TUUD, Local0) + Store (^TUUD, Local0)
- If (LLessEqual (Local0, 0x1000000000)) { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) + If (LLessEqual (Local0, 0x1000000000)) { + Store (0, MMIN) + Store (0, MLEN) + } + Subtract (Add (MMIN, MLEN), 1, MMAX)
- Return (MCRS) + Return (MCRS) + } } -} \ No newline at end of file