Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5696
-gerrit
commit 566381cd1148755e3b7f24fb99c21113d39f4c82 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Thu May 8 19:50:55 2014 +1000
superio/fintek/f71869ad: Fix incorrect LDN's
Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc.
Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/superio/fintek/f71869ad/f71869ad.h | 3 ++- src/superio/fintek/f71869ad/superio.c | 8 +++++--- 2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 3aeac56..c6e8ead 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -29,7 +29,8 @@ #define F71869AD_HWM 0x04 /* Hardware monitor */ #define F71869AD_KBC 0x05 /* PS/2 keyboard and mouse */ #define F71869AD_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71869AD_BSEL 0x07 /* BSEL */ +#define F71869AD_WDT 0x07 /* WDT */ +#define F71869AD_CIR 0x08 /* CIR */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */
#endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..1c10abd 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -99,8 +99,9 @@ static struct device_operations ops = { * irq 0x72 = 12 # Mouse IRQ * end * device pnp 4e.06 off end # GPIO - * device pnp 4e.07 on end # BSEL - * device pnp 4e.0a off end # PME + * device pnp 4e.07 on end # WDT + * device pnp 4e.08 off end # CIR + * device pnp 4e.0a on end # PME * end # f71869ad * */ @@ -112,7 +113,8 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, }, - { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, }, + { &ops, F71869AD_WDT, }, + { &ops, F71869AD_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_PME, }, };