[coreboot-gerrit] Change in coreboot[master]: mb/google/zoombini/variants/meowth: FPMCU interrupt is level-triggered

[Vincent Palatin (Code Review)]

Vincent Palatin has uploaded this change for review. ( https://review.coreboot.org/25110

Change subject: mb/google/zoombini/variants/meowth: FPMCU interrupt is level-triggered
......................................................................

mb/google/zoombini/variants/meowth: FPMCU interrupt is level-triggered

Fix the IRQ configuration: it must be level-sensitive not edge-sensitive
(and match the GPIO configuration).

BUG=b:71986991
BRANCH=none
TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec'
then run 'ectool --name=cros_fp fpmode fingerup' and see the number of
interrupts incrementing and the MKBP event happening.

Signed-off-by: Vincent Palatin

Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d
---
M src/mainboard/google/zoombini/variants/meowth/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/25110/1

diff --git a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
index 2d15c97..7db51be 100644
--- a/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
+++ b/src/mainboard/google/zoombini/variants/meowth/devicetree.cb
@@ -174,7 +174,7 @@
    			register "hid" = "ACPI_DT_NAMESPACE_HID"
    			register "uid" = "1"
    			register "compat_string" = ""google,cros-ec-spi""
-				register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A22_IRQ)"
+				register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)"
    			device spi 0 on end
    		end
    	end # GSPI #1