[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Check TBT & TCSS ports for wake events

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47396 )

Change subject: soc/intel/tigerlake: Check TBT & TCSS ports for wake events
......................................................................

soc/intel/tigerlake: Check TBT & TCSS ports for wake events

Wakes from TBT ports and TCSS devices will show up as PME_B0_STS wakes,
so add checks for wakes from these devices in
pch_log_pme_internal_wake_source.

Signed-off-by: Tim Wawrzynczak 
Change-Id: Ie9904c3c01ea85fcd83218fcfeaa4378b07c1463
---
M src/soc/intel/tigerlake/elog.c
1 file changed, 25 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/47396/1

diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c
index 88324d6..b8b2cc5 100644
--- a/src/soc/intel/tigerlake/elog.c
+++ b/src/soc/intel/tigerlake/elog.c
@@ -76,13 +76,17 @@
    bool dev_found = false;

const struct pme_map ipme_map[] = {
-		{ PCH_DEVFN_HDA, ELOG_WAKE_SOURCE_PME_HDA },
-		{ PCH_DEVFN_GBE, ELOG_WAKE_SOURCE_PME_GBE },
-		{ PCH_DEVFN_SATA, ELOG_WAKE_SOURCE_PME_SATA },
-		{ PCH_DEVFN_CSE, ELOG_WAKE_SOURCE_PME_CSE },
-		{ PCH_DEVFN_XHCI, ELOG_WAKE_SOURCE_PME_XHCI },
-		{ PCH_DEVFN_USBOTG, ELOG_WAKE_SOURCE_PME_XDCI },
-		{ PCH_DEVFN_CNVI_WIFI, ELOG_WAKE_SOURCE_PME_WIFI },
+		{ PCH_DEVFN_HDA,	ELOG_WAKE_SOURCE_PME_HDA },
+		{ PCH_DEVFN_GBE,	ELOG_WAKE_SOURCE_PME_GBE },
+		{ PCH_DEVFN_SATA,	ELOG_WAKE_SOURCE_PME_SATA },
+		{ PCH_DEVFN_CSE,	ELOG_WAKE_SOURCE_PME_CSE },
+		{ PCH_DEVFN_XHCI,	ELOG_WAKE_SOURCE_PME_XHCI },
+		{ PCH_DEVFN_USBOTG,	ELOG_WAKE_SOURCE_PME_XDCI },
+		{ PCH_DEVFN_CNVI_WIFI,	ELOG_WAKE_SOURCE_PME_WIFI },
+		{ SA_DEVFN_TCSS_XHCI,	ELOG_WAKE_SOURCE_PME_TCSS_XHCI },
+		{ SA_DEVFN_TCSS_XDCI,	ELOG_WAKE_SOURCE_PME_TCSS_XDCI },
+		{ SA_DEVFN_TCSS_DMA0,	ELOG_WAKE_SOURCE_PME_TCSS_DMA0 },
+		{ SA_DEVFN_TCSS_DMA1,	ELOG_WAKE_SOURCE_PME_TCSS_DMA1 },
    };

for (i = 0; i < ARRAY_SIZE(ipme_map); i++) {
@@ -106,6 +110,20 @@
    if (!dev_found)
    	dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info());

+	/* Check Thunderbolt ports */
+	if (!dev_found) {
+		for (i = 0; i < NUM_TBT_FUNCTIONS; i++) {
+			const struct device *dev = pcidev_path_on_root(SA_DEVFN_TBT(i));
+			if (!dev)
+				continue;
+
+			if (pci_dev_is_wake_source(dev)) {
+				elog_add_event_wake(ELOG_WAKE_SOURCE_PME_TBT, i);
+				dev_found = true;
+			}
+		}
+	}
+
    if (!dev_found)
    	elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0);
 }