9elements QA has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40840 )
Change subject: soc/intel/jasperlake: Fix 16-bit read/write PCI_COMMAND register
......................................................................
Patch Set 6:
Automatic boot test returned (PASS/FAIL/TOTAL): 4/0/4
Emulation targets:
"QEMU x86 q35/ich9" using payload TianoCore : SUCCESS : https://lava.9esec.io/r/4779
"QEMU x86 q35/ich9" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4778
"QEMU x86 i440fx/piix4" using payload SeaBIOS : SUCCESS : https://lava.9esec.io/r/4777
"QEMU AArch64" using payload LinuxBoot_u-root_kexec : SUCCESS : https://lava.9esec.io/r/4776
Please note: This test is under development and might not be accurate at all!
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I78f091e0d3d17fcfc60cd54721b34d143cbe2d86
Gerrit-Change-Number: 40840
Gerrit-PatchSet: 6
Gerrit-Owner: HAOUAS Elyes
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Gerrit-Reviewer: Nico Huber
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Gerrit-Reviewer: Patrick Georgi
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Gerrit-Reviewer: Patrick Rudolph
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Gerrit-Reviewer: build bot (Jenkins)
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Gerrit-CC: 9elements QA
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Gerrit-CC: Paul Menzel
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Gerrit-Comment-Date: Wed, 03 Jun 2020 13:50:23 +0000
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