Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N.
Hello Kapil Porwal, Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85781?usp=email
to look at the new patch set (#2).
Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ......................................................................
soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
On Panther Lake, the Thunderbolt port index exposed by the LCAP registers begins at 0x15.
The previous offset of 0x10 caused an issue that resulted in:
- Temporary deactivation of Thunderbolt PCI devices during ramstage
- Failure to generate critical ACPI SSDT power management data for the port
This error led to instability in PCIe tunneling during power state transitions.
The offset of 0x15 in Thunderbolt port number was determined through empirical experiments and verified across different SKUs. Document Panther Lake H I/O Registers (#813032) - Link Capabilities (LCAP) - Offset 4c does not provide such information. However, it indicates that the encoding of this register will be scaled according to the number of root ports supported by the platform.
Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/soc/intel/pantherlake/pcie_rp.c 1 file changed, 3 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85781/2