Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48270 )
Change subject: soc/amd/picassso/acpi: increase MMIO region size of GPIO controller ......................................................................
Patch Set 2: Code-Review+2
Patch Set 2:
Patch Set 2:
I'm not seeing it yet. Can you let me know (offline's OK) what doc you're looking at?
see the chapter FCH/registers/GPIO pin control registers/GPIO registers of #55570. There are 4 banks of GPIOs (0-3) and they start 0x100 bytes apart from each other, so 0x400 bytes in total
I assumed you were right, of course. I've always referred to the PMx000 descriptions for the mappings (See "ACPI MMIO Space Allocation"), aka PMx00 in previous generations. Not sure when we added the ability to support a 4th bank, but it looks like someone forgot to update the table.