Nico Huber has uploaded a new patch set (#2). ( https://review.coreboot.org/29481 )
Change subject: [RFC] lib/spd_bin: Redesign API ......................................................................
[RFC] lib/spd_bin: Redesign API
About every two years, somebody reinvents the wheel wrt. SPD handling. Let's break the cycle by providing an API that is simple enough to be used in mainboard code and handles all common patterns (e.g. reading SPDs from CBFS or SMBus).
This is not complete yet, but I wanted to get feedback as early as possible. The rough idea is:
o mainboard code provides a struct with information about where to fetch the SPD from, *per module* (e.g. CBFS, SMBus, memory address) o common code gathers the SPDs and normalizes the struct, so all entries will eventually be memory addresses
The current version uses a simple array to represent the modules. This doesn't reflect the actual topology of memory channels, which is in- stead implied by the consumer of the normalized struct, atm.
This could be extended later, for instance, with a common SPD cache that could be stored along the MRC cache data.
Note that for the latest incarnation, the SPD code of intel/cannonlake, this removes the option to let FSP load the SPD from SMBus. It didn't seem useful, though, as it removes all flexibility. And isn't FSP's responsibility anyway.
Change-Id: Iac300a374e5cd56a9d202cf24ad8fe8367b780d8 Signed-off-by: Nico Huber nico.huber@secunet.com --- M src/Kconfig M src/include/spd_bin.h M src/lib/spd_bin.c M src/mainboard/google/fizz/Kconfig M src/mainboard/google/fizz/romstage.c M src/mainboard/google/kahlee/romstage.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/baseboard/memory.c M src/mainboard/google/zoombini/romstage.c M src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c M src/mainboard/intel/coffeelake_rvp/Kconfig M src/mainboard/intel/coffeelake_rvp/romstage.c M src/mainboard/intel/kblrvp/Kconfig M src/mainboard/intel/kblrvp/romstage.c M src/mainboard/intel/saddlebrook/Kconfig M src/mainboard/intel/saddlebrook/romstage.c M src/mainboard/purism/librem_skl/Kconfig M src/mainboard/purism/librem_skl/romstage.c M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/cnl_memcfg_init.c M src/soc/intel/cannonlake/include/soc/cnl_memcfg_init.h 21 files changed, 277 insertions(+), 241 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/29481/2