Attention is currently required from: Angel Pons.
Keith Hui has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81881?usp=email )
Change subject: nb/sandybridge,sb/bd82x6x: Configure USB from southbridge ......................................................................
nb/sandybridge,sb/bd82x6x: Configure USB from southbridge
Transfer all USB responsibilities to southbridge/intel/bd82x6x, using one set of USB port configurations supplied by mainboards in the southbridge section of their devicetree.
For MRC raminit, export southbridge_fill_pei_data() as a hook for southbridge code to implement. With new code via this hook, bd82x6x fills pei_data based on the one set of USB port config.
For native raminit, early_usb_init() now goes directly to the devicetree for USB port config and no longer get passed an address to it.
TEST=abuild passes for all affected boards. All USB ports still work on asus/p8x7x-series/v/p8z77-m.
Change-Id: I38378c7ee0701abc434b030dd97873f2af63e6b0 Signed-off-by: Keith Hui buurin@gmail.com --- M src/northbridge/intel/sandybridge/pei_data.h M src/northbridge/intel/sandybridge/raminit_mrc.c M src/northbridge/intel/sandybridge/romstage.c M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/early_usb_mrc.c M src/southbridge/intel/bd82x6x/pch.h 6 files changed, 40 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81881/1
diff --git a/src/northbridge/intel/sandybridge/pei_data.h b/src/northbridge/intel/sandybridge/pei_data.h index 0309cf3..db6347c 100644 --- a/src/northbridge/intel/sandybridge/pei_data.h +++ b/src/northbridge/intel/sandybridge/pei_data.h @@ -116,4 +116,5 @@ int ddr_refresh_rate_config; } __packed;
+void southbridge_fill_pei_data(struct pei_data *pei_data); #endif diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 819bfcd..fc64178 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -291,7 +291,7 @@ } }
-static void southbridge_fill_pei_data(struct pei_data *pei_data) +static void sb_fill_pei_data(struct pei_data *pei_data) { const struct device *dev = pcidev_on_root(0x19, 0);
@@ -338,9 +338,6 @@ pei_data->nmode = cfg->nmode; pei_data->ddr_refresh_rate_config = cfg->ddr_refresh_rate_config;
- memcpy(pei_data->usb_port_config, cfg->usb_port_config, - sizeof(pei_data->usb_port_config)); - pei_data->usb3.mode = cfg->usb3.mode; pei_data->usb3.hs_port_switch_mask = cfg->usb3.hs_port_switch_mask; pei_data->usb3.preboot_support = cfg->usb3.preboot_support; @@ -413,6 +410,8 @@ memcpy(&pei_data, &pd, sizeof(pd));
northbridge_fill_pei_data(&pei_data); + sb_fill_pei_data(&pei_data); + /* Have southbridge code fill in USB config data */ southbridge_fill_pei_data(&pei_data); devicetree_fill_pei_data(&pei_data); if (CONFIG(HAVE_SPD_IN_CBFS)) diff --git a/src/northbridge/intel/sandybridge/romstage.c b/src/northbridge/intel/sandybridge/romstage.c index 56dc677..86569c1 100644 --- a/src/northbridge/intel/sandybridge/romstage.c +++ b/src/northbridge/intel/sandybridge/romstage.c @@ -58,7 +58,7 @@
/* When using MRC, USB is initialized by MRC */ if (CONFIG(USE_NATIVE_RAMINIT)) { - early_usb_init(mainboard_usb_ports); + early_usb_init(); }
/* Perform some early chipset init needed before RAM initialization can work */ diff --git a/src/southbridge/intel/bd82x6x/early_usb.c b/src/southbridge/intel/bd82x6x/early_usb.c index 35bfeca..487504b 100644 --- a/src/southbridge/intel/bd82x6x/early_usb.c +++ b/src/southbridge/intel/bd82x6x/early_usb.c @@ -8,8 +8,9 @@ #include <southbridge/intel/common/pmbase.h>
#include "pch.h" +#include "chip.h"
-void early_usb_init(const struct southbridge_usb_port *portmap) +void early_usb_init(void) { u32 reg32; const u32 rcba_dump[8] = { @@ -19,6 +20,9 @@ const u32 currents[] = { USBIR_TXRX_GAIN_MOBILE_LOW, USBIR_TXRX_GAIN_DEFAULT, USBIR_TXRX_GAIN_HIGH, 0x20000f51, 0x2000094a, 0x2000035f, USBIR_TXRX_GAIN_DESKTOP_LOW, 0x20000357, 0x20000353 }; + const struct device *dev = pcidev_on_root(0x1d, 0); + const struct southbridge_intel_bd82x6x_config *config = dev->chip_info; + const struct southbridge_usb_port *portmap = config->usb_port_config; int i;
/* Unlock registers. */ diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index f60cc0b..92ef93a 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -3,6 +3,8 @@ #include <device/pci_ops.h> #include <device/pci_def.h> #include "pch.h" +#include "chip.h" +#include <northbridge/intel/sandybridge/pei_data.h>
#define PCH_EHCI1_TEMP_BAR0 0xe8000000 #define PCH_EHCI2_TEMP_BAR0 0xe8000400 @@ -29,3 +31,30 @@ PCH_EHCI2_TEMP_BAR0); pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } + +/* + * Translate coreboot-formatted USB config data in devicetree + * into a format reference code expects: + * + * [MRC index] = .native_field // what for + * [0] = .enabled // enable + * [1] = .oc_pin // overcurrent pin + * [2] = .current // length + * + * For length, constants are defined and they must be used, as their values differ based on + * whether native or reference code is being used. + */ +void southbridge_fill_pei_data(struct pei_data *pei_data) +{ + const struct device *dev = pcidev_on_root(0x1d, 0); + const struct southbridge_intel_bd82x6x_config *config = dev->chip_info; + + for (unsigned int port = 0; port < ARRAY_SIZE(config->usb_port_config); port++) { + int ocp = config->usb_port_config[port].oc_pin; + if (ocp == -1) + ocp = (port < 8) ? 0 : 4; + pei_data->usb_port_config[port][0] = config->usb_port_config[port].enabled; + pei_data->usb_port_config[port][1] = ocp; + pei_data->usb_port_config[port][2] = config->usb_port_config[port].current; + } +} diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 040b477..17ee4b0 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -64,7 +64,7 @@ void pch_enable(struct device *dev); extern const struct southbridge_usb_port mainboard_usb_ports[14];
-void early_usb_init(const struct southbridge_usb_port *portmap); +void early_usb_init(void);
/* PCI Configuration Space (D30:F0): PCI2PCI */ #define PSTS 0x06