Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/46068 )
Change subject: arch/x86/smbios: Populate SMBIOS type 7 with cache information
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Patch Set 8:
(2 comments)
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@10
PS8, Line 10: Combine L1 Data cache size and
: L1 Instruction cache size
Why?
It seems to be less accurate than what was reported before.
https://review.coreboot.org/c/coreboot/+/46068/8//COMMIT_MSG@11
PS8, Line 11: L1 Instruction cache size, and multiply the cache size of L1 and L2
: by the number of cores
Is there any documentation you followed with these calculations?
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