[coreboot-gerrit] Change in ...coreboot[master]: riscv: Simplify payload handling

[Xiang Wang (Code Review)]

Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31179 )

Change subject: riscv: Simplify payload handling
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/31179/2/src/arch/riscv/boot.c 
File src/arch/riscv/boot.c:

https://review.coreboot.org/#/c/31179/2/src/arch/riscv/boot.c@45 
PS2, Line 45: RISCV_PAYLOAD_MODE_S
If use bbl as rampayload, there should be RISCV_PAYLOAD_MODE_M