[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Set controller state to active in GSPI init

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34449 )

Change subject: soc/intel/common: Set controller state to active in GSPI init
......................................................................

soc/intel/common: Set controller state to active in GSPI init

Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.

BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
     sequence for CML and ICL platforms.

Signed-off-by: Meera Ravindranath 
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) 
Reviewed-by: Subrata Banik 
Reviewed-by: Furquan Shaikh 
Reviewed-by: Aamir Bohra 
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 15 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved
  Subrata Banik: Looks good to me, approved
  Aamir Bohra: Looks good to me, approved

diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c
index 17532bf..beb12fb 100644
--- a/src/soc/intel/common/block/gspi/gspi.c
+++ b/src/soc/intel/common/block/gspi/gspi.c
@@ -23,6 +23,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/chip.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/lpss.h>
 #include <intelblocks/spi.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
@@ -446,8 +447,19 @@
 static int gspi_ctrlr_setup(const struct spi_slave *dev)
 {
    struct spi_cfg cfg;
+	int devfn;
    uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol;
    struct gspi_ctrlr_params params, *p = &params;
+	const struct device *device;
+
+	devfn = gspi_soc_bus_to_devfn(dev->bus);
+	if (devfn < 0) {
+		printk(BIOS_ERR, "%s: No GSPI controller found on SPI bus %u.\n",
+			__func__, dev->bus);
+		return -1;
+	}
+
+	device = pcidev_path_on_root(devfn);

/* Only chip select 0 is supported. */
    if (dev->cs != 0) {
@@ -466,6 +478,9 @@
    	return -1;
    }

+	/* Ensure controller is in D0 state */
+	lpss_set_power_state(device, STATE_D0);
+
    /* Take controller out of reset, keeping DMA in reset. */
    gspi_write_mmio_reg(p, RESETS, CTRLR_ACTIVE | DMA_RESET);